Intermetal dielectric layers are commonly used to isolate conducting structures, such as metal layers, from subsequently deposited conducting layers. Intermetal dielectric layers are also useful in performing a planarization function. Typical prior art processes for forming an intermetal dielectric layer consist of depositing multiple layers of oxide over the underlying metal layer.
In one typical prior art process, a thick liner oxide composed of silicon dioxide first covers the metal layer, followed by a low dielectric material layer that is baked and cured. A chemical mechanical polishing (CMP) is performed on the cured low dielectric material layer. A second silicon dioxide layer completes the intermetal dielectric layer. A planarization process, such as CMP, is performed to improve the global planarization of the intermetal dielectric layer. The multiple layers of oxide are then patterned and etched to form via holes through to the underlying metal layer.
This prior art method for forming an intermetal dielectric layer presented many problems. The removal rate of the low dielectric material layer during CMP is very low. Endpoint detection is not available. In addition, the intermetal capacitance is high due to the thick liner oxide.
Another prior art process involves the same steps as the first prior art process discussed immediately above except the step of CMP on the cured low dielectric material layer is omitted. This prior art method also presented many problems. Similar to the first prior art process discussed above, endpoint detection is not available. In addition, this prior art process raises poisoned via concerns. Furthermore, the low dielectric material is present on the top of the conducting structures because CMP is not performed on the cured low dielectric material layer, and the thermal conductivity of the low dielectric material is low.
What is needed is a method for forming a planarized intermetal dielectric layer that eliminates the aforementioned problems.